1. Field of the Invention
The present invention relates generally to non-volatile memory devices, and more particularly, to zero-power electrically erasable and programmable memory cells, such as EEPROM cells.
2. Discussion of the Related Art
Referring to FIG. 1, an example programmable logic device is a programmable AND gate 100 of the prior art. The programmable AND gate 100 includes a first input node 102 for inputting a first input signal, A, and a second input node 104 for inputting a second input signal, B. The first input signal, A, is coupled through a first inverter 106 and a second inverter 108 to the gate of a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) 110. The complement of the first input signal, designated as A*, (i.e., the output of the first inverter 106) is coupled to the gate of a second NMOSFET (N-channel metal oxide semiconductor field effect transistor) 112.
Similarly, the second input signal, B, is coupled through a third inverter 114 and a fourth inverter 116 to the gate of a third NMOSFET (N-channel metal oxide semiconductor field effect transistor) 118. The complement of the second input signal, designated as B*, (i.e., the output of the third inverter 114) is coupled to the gate of a fourth NMOSFET (N-channel metal oxide semiconductor field effect transistor) 120.
A first programmable switch 122 is coupled between the drain of the first NMOSFET 110 and an output node 130, and a second programmable switch 124 is coupled between the drain of the second NMOSFET 112 and the output node 130. Similarly, a third programmable switch 126 is coupled between the drain of the third NMOSFET 118 and the output node 130, and a fourth programmable switch 128 is coupled between the drain of the fourth NMOSFET 120 and the output node 130. In addition, a current source 132 is coupled to the output node 130 for charging the output node 130 when the output signal at the output node 130 turns to a logical high state.
For operation of the programmable AND gate 100 of FIG. 1, the first, second, third, and fourth switches 122, 124, 126, and 128 are programmable to be switched open or closed. One of the first and second programmable switches 122 and 124 is programmed to be open, and the other is programmed to be closed. Similarly, one of the third and fourth programmable switches 126 and 128 is programmed to be open, and the other is programmed to be closed.
The output node 130 of the programmable AND gate 100 provides an AND operation (of one of the first input signal, A, or the complement of the first input signal, A*, and one of the second input signal, B, or the complement of the second input signal, B*. If the first switch 122 is programmed to be closed with the second switch 124 being programmed to be open, then the programmable AND gate 100 provides an AND operation with the complement of the first input signal, A*, instead of the first input signal, A. On the other hand, if the first switch 122 is programmed to be open with the second switch 124 being programmed to be closed, then the programmable AND gate 100 provides an AND operation with the first input signal, A, instead of the complement of the first input signal, A*.
Similarly, if the third switch 126 is programmed to be closed with the fourth switch 128 being programmed to be open, then the programmable AND gate 100 provides an AND operation with the complement of the second input signal, B*, instead of the second input signal, B. On the other hand, if the third switch 126 is programmed to be open with the fourth switch 128 being programmed to be closed, then the programmable AND gate 100 provides an AND operation with the second input signal, B, instead of the complement of the second input signal, B*.
Thus, in the example illustration of FIG. 1, since the first switch 122 is programmed to be closed while the second switch 124 is programmed to be open, the programmable AND gate 100 provides an AND operation with the complement of the first input signal, A*, instead of the first input signal, A. Also, since the third switch 126 is programmed to be open while the fourth switch 128 is programmed to be closed, the programmable AND gate 100 provides an AND operation with the second input signal, B, instead of the complement of the second input signal, B*.
Thus, the output node 130 provides an output signal=A*xc2x7B. Referring to FIG. 1, only in the case when the first input signal, A, is a logical low state and the second input signal, B, is a logical high state, all of the first, second, third, and fourth NMOSFETs 110, 112, 118, and 120 do not conduct current away from the output node 130. Thus, the current from the current source 132 charges up the output node 130 to a logical high state in that case. For any other logical states of the first and second input signals, A and B, at least one of the first NMOSFET 110 and the fourth NMOSFET 120 conducts current out of the output node 130 to couple the output node 130 to ground such that a logical low state is formed at the output node 130.
In the prior art programmable AND gate 100 of FIG. 1, a constant amount of current from the current source 132 is dissipated when at least one of the first NMOSFET 110 and the fourth NMOSFET 120 conducts current out of the output node 130 to couple the output node 130 to ground. Such constant current flow results in disadvantageous power dissipation. In addition, device dimensions are constantly scaled down with advancement of IC (integrated circuit) technology. However, as supply voltages are further scaled down along with device dimensions, the noise margin of the prior art programmable AND gate 100 of FIG. 1 disadvantageously decreases to deteriorate the performance of the AND gate 100. In addition, the steady state current of the current source 132 does not necessarily scale down with device dimensions such that the prior art programmable AND gate 100 of FIG. 1 still has disadvantageous steady state power dissipation even with scaling down of device dimensions.
Thus, a mechanism is desired for implementing programmable logic devices such as programmable AND gates and programmable OR gates with minimized static power dissipation and with further scalability of device dimensions and supply voltages.
Accordingly, in a general aspect of the present invention, a zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. Such a zero-power electrically erasable and programmable memory cell may advantageously form part of programmable logic devices such as programmable AND, OR, NAND, or NOR gates with minimized static power dissipation.
According to a general embodiment for an electrically erasable and programmable zero-power memory cell, a P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. A drain of the P-channel sense transistor is coupled to a drain of the N-channel sense transistor to form an output of the memory cell, and a gate of the P-channel sense transistor is coupled to a gate of the N-channel sense transistor to form a floating gate of the memory cell. In addition, a write transistor has a source coupled to a WBL (write bit line) and has a gate coupled to a WL (write line). A tunneling capacitor is coupled between the floating gate of the memory cell and a drain of the write transistor, and a coupling capacitor is coupled between a CG (control gate) node and the floating gate of the memory cell.
The CG (control gate) node is biased with a positive voltage during an erase operation, and the WBL (write bit line) and the WL (write line) are biased to turn on the write transistor such that a negative voltage forms on the floating gate of the memory cell by charge tunneling through the tunneling capacitor. In that case, the P-channel sense transistor turns on for forming a logical high state at the output of the memory cell during the erase operation. Alternatively, the CG (control gate) node is biased with a ground or negative voltage during a program operation, and the WBL (write bit line) and the WL (write line) are biased to turn on the write transistor such that a positive voltage forms on the floating gate of the memory cell by charge tunneling through the tunneling capacitor. In that case, the N-channel sense transistor turns on for forming a logical low state at the output of the memory cell during the program operation.
In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation.
In another embodiment of the present invention, a magnitude of the respective threshold voltage of each of the P-channel and N-channel sense transistors is higher than a magnitude of a threshold voltage of standard process P-channel and N-channel transistors. For example, a sum of a magnitude of a respective threshold voltage of the P-channel sense transistor and a magnitude of a respective threshold voltage of the N-channel sense transistor is greater than a minimum value in a range of a difference of a first voltage generated by the first voltage generator and a second voltage generated by the second voltage generator during a read operation of the memory cell. In that case, the thickness of the respective gate oxide for each of the P-channel and N-channel sense transistors is for a high voltage MOSFET, and the concentration of the respective channel doping for each of the P-channel and N-channel sense transistors is for a low voltage MOSFET. With such a higher threshold voltage, the P-channel and N-channel sense transistors do not erroneously turn on to dissipate power during the read operation, to ensure that the memory cell is a zero-power memory cell.
The zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology when the P-channel sense transistor is comprised of a PMOSFET (P-channel metal oxide semiconductor field effect transistor), and when the N-channel sense transistor and the write transistor are comprised of NMOSFETs (N-channel metal oxide semiconductor field effect transistors).
In this manner, the zero-power electrically erasable and programmable memory cell of the present invention is implemented in CMOS technology without use of any current source. Rather, the electrically erasable and programmable memory cell of the present invention operates to provide logic levels with zero power dissipation. In addition, the electrically erasable and programmable memory cell implemented in CMOS technology in the present invention is further scalable.